There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays, among others. CCDs are often employed for image acquisition and enjoy a number of advantages, which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer, which also results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital imaging applications.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit, for example, includes a focal plane array of pixel cells; each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A typical readout circuit in each pixel cell includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line; however other readout circuit configurations are possible. The pixel cell also may have a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion node. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion node for charge conversion to a voltage and another transistor for resetting the floating diffusion node to a predetermined charge level prior to charge transference.
In a CMOS imager pixel cell, for example, a four transistor (4T) pixel, all the active elements of a pixel cell perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion node; (3) resetting the floating diffusion node to a known state before the transfer of charge to it; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The so-called three transistor (3T) pixel circuit operates similarly, but connects the photosensor directly to the source follower.
CMOS imagers are generally known and are discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046–2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452–453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, all of which are herein incorporated by reference.
FIG. 1 illustrates a block diagram of a conventional CMOS imager device 308 having an array 200 of pixel cells, which may be 3T, 4T or pixels using other numbers of transistors. Pixel cell array 200 comprises a plurality of pixel cells arranged in a predetermined number of columns and rows. The pixel cells of each row in array 200 are all turned on at the same time by a row select line, and the pixel cells of each column are selectively output by respective column select lines. The row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270. The CMOS imager is operated by the control circuit 250 that controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel operation and readout, and row and column driver circuitry 210, 260 that apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically each include a pixel reset signal, Vrst and a pixel image signal, Vsig, for a pixel cell selectively connected to a column line are read by a sample and hold circuit 261 associated with the column driver 260 and are subtracted by amplifier 262 to form a differential signal Vrst−Vsig for each pixel cell which is amplified and then digitized by analog to digital converter 275. The analog to digital converter 275 converts the received analog pixel signals to digital signals, which are fed to an image processor 280 to form a digital image.
The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19–29 1994; Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(2), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95 pages 17–25 (1995) as well as other publications. These references are incorporated herein by reference.
Imager arrays are typically tested to determine the signal to noise ratio for each pixel cell or a row or column of pixel cells. In addition, when pixel cells receive an input signal, some of the input signal is also received by adjacent pixel cells. The spread of an input signal to adjacent pixel cells causes the adjacent pixel cells to incorrectly sense light intensity from a received image. Accordingly, the amount of such adjacent pixel cell spread is an important parameter to consider in the design and fabrication of a pixel cell array. The amount of spread of an input signal to adjacent pixel cells, carrier diffusion (electrical crosstalk), can be determined by the modulation transfer function (MTF) of the imager array, which is an effective measurement of the sharpness and spatial resolution for the imager array. The greater the carrier diffusion, the lower the sharpness and resolution for the imager array. The MTF for an imager array can also be calculated using measurements of input signal reflection, interference or scattering as the input signal passes through various layers, i.e. metal, microlens, etc., of the imager array (optical crosstalk). This MTF is a value of interest for imager arrays in general, including both CCD and CMOS arrays, among others.
A current method for testing MTF for image sensor arrays involves measuring the edge response of the imager array by applying an image signal to the image array that has a dark image section adjacent to a light image section. The edge between the dark and light sections is lined up exactly between two adjacent pixel columns in the imager array and the MTF is calculated as follows:MTF=(A−B)/(C−D)
where A=the pixel value on the light side of the edge;
B=the pixel value on the dark side of the edge;
C=the pixel value on the light side away from the edge; and
D=the pixel value on the dark side away from the edge.
This formula compares the degraded contrast at the light/dark edge to the maximum contrast of the sensor (totally dark signal−totally bright or saturated signal). The test typically uses an entire column of pixel cells, which are averaged, instead of an individual pixel cell in order to avoid erroneous aberrations of individual pixel cells.
It is difficult to automate the above-described testing method for several reasons. Such testing is generally performed during probe, where various tests are automatically performed to determine acceptable and failing parts. During probe the alignment of the dark and light edge of an input image exactly between two adjacent columns of pixel cells of an imager array is complex since, for example, rotation of the die and input image have to be the same. Accordingly, there is a need and desire for a better method of measuring the MTF of pixel array imagers.